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400 msps 14-bit, 1.8 v cmos direct digital synthesizer ad9952 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2003 analog devices, inc. all rights reserved. features 400 msps internal clock speed integrated 14-bit dac 32-bit tuning word phase noise C120 dbc/hz @ 1 khz offset (dac output) excellent dynamic performance >80 db sfdr @ 160 mhz (100 khz offset) a out serial i/o control 1.8 v power supply software and hardware controlled power-down 48-lead tqfp/ep package support for 5 v input levels on most digital inputs pll refclk multiplier (4 to 20) internal oscillator, can be driven by a single crystal phase modulation capability multichip synchronization high speed comparator (200 mhz toggle rate) applications agile lo frequency synthesis programmable clock generators test and measurement equipment acousto-optic device drivers functional block diagram cos(x) control registers oscillator/buffer sync enable i/o update dac_r set dds core phase offset phase accumulator z ?1 z ?1 iout iout osk pwrdwnctl refclk refclk crystal out i/o port dds clock frequency tuning word clear phase accumulator amplitude scale factor dac system clock system clock sync_in sync_clk reset timing and control logic 4 ?20 clock multiplier 4 ad9952 32 32 14 14 19 14 0 m u x m u x 03358-0-001 comparator comp_out comp_in comp_in figure 1.
ad9952 rev. 0 | page 2 of 28 table of contents general description ......................................................................... 3 ad9952electrical sp ecifications ................................................ 4 absolute maximum ratings............................................................ 7 pin configuration............................................................................. 8 pin function descriptions .............................................................. 9 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 13 component blocks ..................................................................... 13 modes of operation ................................................................... 18 programming ad9952 features............................................... 18 serial port operation................................................................. 21 instruction byte .......................................................................... 23 serial interface port pin description....................................... 23 msb/lsb transfers .................................................................... 23 suggested application circuits..................................................... 25 outline dimensions ....................................................................... 26 esd caution................................................................................ 26 ordering guide .......................................................................... 26 revision history revision 0: initial version
ad9952 rev. 0 | page 3 of 28 general description the ad9952 is a direct digital synthesizer (dds) featuring a 14-bit dac operating up to 400 msps. the ad9952 uses advanced dds technology, coupled with an internal high speed, high performance dac to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform at up to 200 mhz. the ad9952 is designed to provide fast frequency hopping and fine tuning resolution (32-bit frequency tuning word). the frequency tuning and control words are loaded into the ad9952 via a serial i/o port. the ad9952 is specified to operate over the extended industrial temperature range of C40c to +105c.
ad9952 rev. 0 | page 4 of 28 electrical specifications table 1. unless otherwise noted, avdd, dvdd = 1.8 v 5%, dvdd_i/o = 3.3 v 5%, r set = 3.92 k?, external reference clock frequency = 20 mhz with refclk multiplier enabled at 20 . dac output must be referenced to avdd, not agnd. parameter temp min typ max unit ref clock input characteristics frequency range refclk multiplier disabled full 1 400 mhz refclk multiplier enabled at 4 full 20 100 mhz refclk multiplier enabled at 20 full 4 20 mhz input capacitance 25c 3 pf input impedance 25c 1.5 k? duty cycle 25c 50 % duty cycle with refclk multiplier enabled 25c 35 65 % refclk input power 1 full C15 0 +3 dbm dac output characteristics resolution 14 bits full-scale output current 25c 5 10 15 ma gain error 25c C10 +10 %fs output offset 25c 0.6 a differential nonlinearity 25c 1 lsb integral nonlinearity 25c 2 lsb output capacitance 25c 5 pf residual phase noise @ 1 khz offset, 40 mhz a out refclk multiplier enabled @ 20 25c C105 dbc/hz refclk multiplier enabled @ 4 25c C115 dbc/hz refclk multiplier disabled 25c C132 dbc/hz voltage compliance range 25c avdd C 0.5 avdd + 0.5 v wideband sfdr 1 mhz to 10 mhz analog out 25c 73 dbc 10 mhz to 40 mhz analog out 25c 67 dbc 40 mhz to 80 mhz analog out 25c 62 dbc 80 mhz to 120 mhz analog out 25c 58 dbc 120 mhz to 160 mhz analog out 25c 52 dbc narrow-band sfdr 40 mhz analog out (1 mhz) 25c 87 dbc 40 mhz analog out (250 khz) 25c 89 dbc 40 mhz analog out (50 khz) 25c 91 dbc 40 mhz analog out (10 khz) 25c 93 dbc 80 mhz analog out (1 mhz) 25c 85 dbc 80 mhz analog out (250 khz) 25c 87 dbc 80 mhz analog out (50 khz) 25c 89 dbc 80 mhz analog out (10 khz) 25c 91 dbc 120 mhz analog out (1 mhz) 25c 83 dbc 120 mhz analog out (250 khz) 25c 85 dbc 120 mhz analog out (50 khz) 25c 87 dbc 120 mhz analog out (10 khz) 25c 89 dbc 160 mhz analog out (1 mhz) 25c 81 dbc 160 mhz analog out (250 khz) 25c 83 dbc 160 mhz analog out (50 khz) 25c 85 dbc 160 mhz analog out (10 khz) 25c 87 dbc
ad9952 rev. 0 | page 5 of 28 parameter temp min typ max unit comparator input characteristics input capacitance 25c 3 pf input resistance 25c 500 k? input current 25c 12 a hysteresis 25c 30 45 ma comparator output characteristics logic 1 voltage, high z load full 1.6 v logic 0 voltage, high z load full 0.4 v propagation delay 25c 3 ns output duty cycle error 25c 5 % rise/fall time, 5 pf load 25c 1 ns toggle rate, high z load 25c 200 mhz output jitter 2 25c 1 ps rms comparator narrow-band sfdr 10 mhz (1 mhz) 25c 80 dbc 10 mhz (250 khz) 25c 85 dbc 10 mhz (50 khz) 25c 90 dbc 10 mhz (10 khz) 25c 95 dbc 70 mhz (1 mhz) 25c 80 dbc 70 mhz (250 khz) 25c 85 dbc 70 mhz (50 khz) 25c 90 dbc 70 mhz (10 khz) 25c 95 dbc 110 mhz (1 mhz) 25c 80 dbc 110 mhz (250 khz) 25c 85 dbc 110 mhz (50 khz) 25c 90 dbc 110 mhz (10 khz) 25c 95 dbc 140 mhz (1 mhz) 25c 80 dbc 140 mhz (250 khz) 25c 85 dbc 140 mhz (50 khz) 25c 90 dbc 140 mhz (10 khz) 25c 95 dbc 160 mhz (1 mhz) 25c 80 dbc 160 mhz (250 khz) 25c 85 dbc 160 mhz (50 khz) 25c 90 dbc 160 mhz (10 khz) 25c 95 dbc clock generator output jitter 3 5 mhz a out 25c 100 ps rms 10 mhz a out 25c 60 ps rms 40 mhz a out 25c 50 ps rms 80 mhz a out 25c 50 ps rms 120 mhz a out 25c 50 ps rms 140 mhz a out 25c 50 ps rms 160 mhz a out 25c 50 ps rms timing characteristics serial control bus maximum frequency full 25 mbps minimum clock pulse width low full 7 ns minimum clock pulse width high full 7 ns maximum clock rise/fall time full 2 ns minimum data setup time dv dd_i/o = 3.3 v full 3 ns minimum data setup time dv dd_i/o = 1.8 v full 5 ns minimum data hold time full 0 ns maximum data valid time full 25 ns
ad9952 rev. 0 | page 6 of 28 parameter temp min typ max unit wake-up time 4 full 1 ms minimum reset pulse width high full 5 sysclk cycles 5 i/o update to sync_clk setup time dvdd_i/o = 3.3 v full 4 ns i/o update to sync_clk setup time dvdd_i/o = 3.3 v full 6 ns i/o update, sync_clk hold time full 0 ns latency i/o update to frequency change pr op delay 25c 24 sysclk cycles i/o update to phase offset change prop delay 25c 24 sysclk cycles i/o update to amplitude change pr op delay 25c 16 sysclk cycles cmos logic inputs logic 1 voltage @ dvdd_i/o (pin 43) = 1.8 v 25c 1.25 v logic 0 voltage @ dvdd_i/o (pin 43) = 1.8 v 25c 0.6 v logic 1 voltage @ dvdd_i/o (pin 43) = 3.3 v 25c 2.2 v logic 0 voltage @ dvdd_i/o (pin 43) = 3.3 v 25c 0.8 v logic 1 current 25c 3 12 a logic 0 current 25c 12 a input capacitance 25c 2 pf cmos logic outputs (1 ma load) dvdd_i/o = 1.8 v logic 1 voltage 25c 1.35 v logic 0 voltage 25c 0.4 v cmos logic outputs (1 ma load) dvdd_i/o = 3.3 v logic 1 voltage 25c 2.8 v logic 0 voltage 25c 0.4 v power consumption (avdd = dvdd = 1.8 v) single-tone mode 25c 162 171 mw rapid power-down mode 25c 150 160 mw full-sleep mode 25c 20 27 mw synchronization function 6 maximum sync clock rate (dvdd_i/o = 1.8 v) 25c 62.5 mhz maximum sync clock rate (dvdd_i/o = 3.3 v) 25c 100 mhz sync_clk alignment resolution 7 25c 1 sysclk cycles 1 to achieve the best possible phase noise, the largest amplitude clock possible should be used. reducing the clock input amplit ude will reduce the phase noise performance of the device. 2 represents the cycle-to-cycle residual jitter from the comparator alone. 3 represents the cycle-to-cycle residual jitter from the dds core driving the comparator. 4 wake-up time refers to the recovery from analog power-do wn modes (se e the power-down functions of the ad9952 section). the lon gest time requir ed is for the reference clock multiplier pll to relock to the reference. the wake-up time assumes there is no capacitor on dacbp and that the recommended pll loop filter values are used. 5 sysclk cycle refers to the actual clock frequency used on-chip by the dds. if the reference clock multiplier is used to multip ly the external reference clock frequency, the sysclk frequency is the external frequency multiplied by the reference clock multiplication factor. if the reference clock multiplier is not used, the sysclk frequency is the same as the external reference clock frequency. 6 sync_clk = ? sysclk rate. for sync_clk rates 50 mhz, the high speed sync enable bit, cfr2<11>, should be set. 7 this parameter indicates that the digital synchronization feature canno t overcome phase delays (timing skew) between system cl ock rising edges. if the system clock edges are aligned, the synchronizat ion function should not increase the skew between the two edges.
ad9952 rev. 0 | page 7 of 28 absolute maximum ratings table 2. parameter rating maximum junction temperature 150c dvdd_i/o (pin 43) 4 v avdd, dvdd 2 v digital input voltage (dvdd_i/o = 3.3 v) C0.7 v to +5.25 v digital input voltage (dvdd_i/o = 1.8 v) C0.7 v to +2.2 v digital output current 5 ma storage temperature C65c to +150c operating temperature C40c to +105c lead temperature (10 sec soldering) 300c ja 38c/w jc 15c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 03374-0-032 iout iout must terminate outp uts to av dd for current flow. do not exceed the output voltage compliance rating. dac outputs avdd comparator outp ut dvdd_i/o input digital inputs avoid overdriving digital inputs. forward biasing esd diodes may couple digital noise onto power pins. avdd comp in comp in comparator inputs figure 2. equivalent input and output circuits
ad9952 rev. 0 | page 8 of 28 pin configuration 43 42 41 40 39 38 37 48 47 46 45 44 13 15 16 17 18 19 20 21 22 23 24 i/o update dvdd dgnd avdd agnd avdd agnd osc/refclk osc/refclk crystal out clkmodeselect loop_filter agnd avdd agnd avdd agnd avdd iout avdd iout dacbp agnd osk dvdd dvdd sync_cl k sync_in dvdd_i/o sclk dgnd sdio sdo cs iosync reset pwrdwnctl dvdd dgnd agnd comp_in comp_in avdd comp_out avdd agnd avdd ad9952 top view (not to scale) 14 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 03358-0-002 dac_r set figure 3. 48-lead tqfp/ep note that the exposed paddle on the bottom of the package forms an electrical connection for the dac and must be attached to analog ground. note that pin 43, dvdd_i/o, can be powered to 1.8 v or 3.3 v; however, the dvdd pins (pin 2 and pin 34) can only be powered to 1.8 v.
ad9952 rev. 0 | page 9 of 28 pin function descriptions table 3. 48-lead tqfp/ep pin no. mnemonic i/o description 1 i/o update i the rising edge transfers the contents of the inte rnal buffer memory to the i/o registers. this pin must be set up and held arou nd the sync_clk output signal. 2, 34 dvdd i digital power supply pins (1.8 v). 3, 33, 42, 47, 48 dgnd i digital power ground pins. 4, 6, 13, 16, 18, 19, 25, 27, 29 avdd i analog power supply pins (1.8 v). 5, 7, 14, 15, 17, 22, 26, 32 agnd i analog power ground pins. 8 osc /refclk i complementary reference clock/oscillator input. when the refclk port is operated in single- ended mode, refclk should be decoupled to avdd with a 0.1 f capacitor. 9 osc/refclk i reference clock/oscillator input. see clock in put section for details on the oscillator/refclk operation. 10 crystal out o output of the oscillator section. 11 clkmodeselect i control pin for the oscillator section. when high, th e oscillator section is enabled. when low, the oscillator section is bypassed. 12 loop_filter i this pin provides the connection for the extern al zero compensation network of the refclk multipliers pll loop filter. the network consists of a 1 k? resistor in series with a 0.1 f capacitor tied to avdd. 20 iout o complementary dac output. should be bias ed through a resistor to avdd, not agnd. 21 iout o dac output. should be biased through a resistor to avdd, not agnd. 23 dacbp i dac biasline decoupling pin. 24 dac_r set i a resistor (3.92 k? nominal) connected from agnd to dac_r set establishes the reference current for the dac. 28 comp_out o comparator output. 30 comp_in i compator input. 31 comp_in i compartor complementary input 35 pwrdwnctl i input pin used as an external power-down cont rol (see table 8 for details). 36 reset i active high hardware reset pin. assertion of the reset pin forces the ad9952 to the initial state, as described in the i/o port register map. 37 iosync i asynchronous active high reset of the serial port controller. when high, the current i/o operation is immediately terminated, enabling a new i/o operation to commence once iosync is returned low. if unused, ground this pi n; do not allow this pin to float. 38 sdo o when operating the i/o port as a 3-wire serial port, this pin serves as the se rial data output. when operated as a 2-wire serial port, this pi n is unused and can be left unconnected. 39 cs i this pin functions as an active low chip select that allows multiple devices to share the i/o bus. 40 sclk i this pin functions as the serial data clock for i/o operations. 41 sdio i/o when operating the i/o port as a 3-wire serial port , this pin serves as the serial data input only. when operated as a 2-wire serial port, this pin is the bidirectional serial data pin. 43 dvdd_i/o i digital power supply (for i/o cells only, 3.3 v). 44 sync_in i input signal used to synchronize multiple ad 9952s. this input is connected to the sync_clk output of a master ad9952. 45 sync_clk o clock output pin that serves as a synchronizer for external hardware. 46 osk i input pin used to control the direction of the shaped on-off keying function when programmed for operation. osk is synchronous to the sync_clk pin. when osk is not programmed, this pin should be tied to dgnd. <49> agnd i the exposed paddle on the bottom of the package is a ground connection for the dac and must be attached to agnd in any board layout.
ad9952 rev. 0 | page 10 of 28 typical performance characteristics center 100mhz #res bw 3khz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 3khz span 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 98.0mhz ?70.68db 1 1r 03374-0-016 marker 100.000000mhz ?70.68db figure 4. f out = 1 mhz fclk = 400 msps, wbsfdr center 100mhz #res bw 3khz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 3khz span 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 80.0mhz ?69.12db 1 1r 03374-0-017 marker 80.000000mhz ?69.12db figure 5. f out = 10 mhz, fclk = 400 msps, wbsfdr center 100mhz #res bw 3khz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 3khz span 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 0hz ?68.44db 1 1r 03374-0-018 marker 40.000000mhz ?68.44db figure 6. f out = 40 mhz, fclk = 400 msps, wbsfdr center 100mhz #res bw 3khz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 3khz span 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 80.0mhz ?61.55db 1 1r 03374-0-019 marker 80.000000mhz ?61.55db figure 7. f out = 80 mhz fclk = 400 msps, wbsfdr center 100mhz #res bw 3khz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 3khz span 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 40.0mhz ?56.2db 1 1r 03374-0-020 marker 40.000000mhz ?56.2db figure 8. f out = 120 mhz, fclk = 400 msps, wbsfdr center 100mhz #res bw 3khz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 3khz span 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 0hz ?53.17db 1 1r 03374-0-021 marker 80.000000mhz ?53.17db figure 9. f out = 160 mhz, fclk = 400 msps, wbsfdr
ad9952 rev. 0 | page 11 of 28 center 1.105mhz #res bw 30hz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 30hz span 2mhz sweep 199.2 s (401 pts) w1 s2 s3 fc aa st ref ?4dbm pea k log 10db/ atten 10db mkr1 1.105mhz ?5.679dbm 1 03374-0-022 marker 1.105000mhz ?5.679dbm figure 10. f out = 1.1 mhz, fclk = 400 msps, nbsfdr, 1 mhz center 10mhz #res bw 30hz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 30hz span 2mhz sweep 199.2 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 85khz ?93.01db 1 1r 03374-0-023 marker 40.000000mhz ?56.2db figure 11. f out = 10 mhz, fclk = 400 msps, nbsfdr, 1 mhz center 39.9mhz #res bw 30hz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 30hz span 2mhz sweep 199.2 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 39.905mhz ?5.347dbm 1 03374-0-024 marker 39.905000mhz ?5.347dbm figure 12. f out = 39.9 mhz, fclk = 400 msps, nbsfdr, 1 mhz center 80.25mhz #res bw 30hz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 30hz span 2mhz sweep 199.2 s (401 pts) w1 s2 s3 fc aa st ref ?4dbm pea k log 10db/ atten 10db mkr1 80.301mhz ?6.318dbm 1 03374-0-025 marker 80.301000mhz ?6.318dbm figure 13. f out = 80.3 mhz, fclk = 400 msps, nbsfdr, 1 mhz center 120.2mhz #res bw 30hz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 30hz span 2mhz sweep 199.2 s (401 pts) w1 s2 s3 fc aa st ref ?4dbm pea k log 10db/ atten 10db mkr1 120.205mhz ?6.825dbm 1 03374-0-026 marker 120.205000mhz ?6.825dbm figure 14. f out = 120.2 mhz, fclk = 400 msps, nbsfdr, 1 mhz center 160.5mhz #res bw 30hz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 30hz span 2mhz sweep 199.2 s (401 pts) w1 s2 s3 fc aa st ref ?4dbm pea k log 10db/ atten 10db mkr1 600khz ?0.911db 1 03374-0-027 center 160.5000000mhz figure 15. f out = 160 mhz, fclk = 400 msps, nbsfdr, 1 mhz
ad9952 rev. 0 | page 12 of 28 figure 16. residual phase noise with f out = 159.5 mhz, f clk = 400 msps (green), 4 100 msps (red), and 20 20 msps (blue) ch1 200mv ? 1 it 4.0ps/pt 3.1ns m 200ps 20.0gs/s a ch1 708mv 03374-0-031 t 1 = 3.156ns t 2 = 3.04ns ? t = ?116.0ps 1/ ? t = ?8.621ghz figure 17. residual peak-to-peak jitter of dds and comparator operating together at 160 mhz figure 18. residual phase noise with f out = 9.5 mhz, f clk = 400 msps (green), 4 100 msps (red), and 20 20 msps (blue) ref2 200mv 500ns r2 r1 it 10.0ps/pt ?100ps m 500ps 20.0gs/s a ch1 708mv 03374-0-030 fall (r1) = 396.4ps rise(r2) = 464.3ps figure 19. comparator rise and fall time at 160 mhz
ad9952 rev. 0 | page 13 of 28 theory of operation component blocks dds core the output frequency ( f o ) of the dds is a function of the frequency of the system clock (sysclk), the value of the frequency tuning word ( ftw ), and the capacity of the accumulator (2 32 , in this case). the exact relationship is given below with f s defined as the frequency of sysclk. () () 31 32 2 0 2 / = ftw with f ftw f s o () () 1 C 2 2 2 / C 1 32 31 32 < < = ftw with ftw f f s o the value at the output of the phase accumulator is translated to an amplitude value via the cos(x) functional block and routed to the dac. in certain applications, it is desirable to force the output signal to zero phase. simply setting the ftw to 0 does not accomplish this; it only results in the dds core holding its current phase value. thus, a control bit is required to force the phase accumu- lator output to zero. at power-up, the clear phase accumulator bit is set to logic 1, but the buffer memory for this bit is cleared (logic 0). there- fore, upon power-up, the phase accumulator will remain clear until the first i/o update is issued. phase-locked loop (pll) the pll allows multiplication of the refclk frequency. con- trol of the pll is accomplished by programming the 5-bit refclk multiplier portion of control function register no. 2, bits <7:3>. when programmed for values ranging from 0x04 to 0x14 (4 decimal to 20 decimal), the pll multiplies the refclk input frequency by the corresponding decimal value. however, the maximum output frequency of the pll is restricted to 400 mhz. whenever the pll value is changed, the user should be aware that time must be allocated to allow the pll to lock (approximately 1 ms). the pll is bypassed by programming a value outside the range of 4 to 20 (decimal). when bypassed, the pll is shut down to conserve power. clock input the ad9952 supports various clock methodologies. support for differential or single-ended input clocks and enabling of an on-chip oscillator and/or a phase-locked loop (pll) multiplier is all controlled via user programmable bits. the ad9952 may be configured in one of six operating modes to generate the system clock. the modes are configured using the clkmode- select pin, cfr1<4>, and cfr2<7:3>. connecting the exter- nal pin clkmodeselect to logic high enables the on-chip crystal oscillator circuit. with the on-chip oscillator enabled, users of the ad9952 connect an external crystal to the refclk and refclkb inputs to produce a low frequency reference clock in the range of 20 mhz to 30 mhz. the signal generated by the oscillator is buffered before it is delivered to the rest of the chip. this buffered signal is available via the crystal out pin. bit cfr1<4> can be used to enable or disable the buffer, turning on or off the system clock. the oscillator itself is not powered down in order to avoid long start-up times associ- ated with turning on a crystal oscillator. writing cfr2<9> to logic high enables the crystal oscillator output buffer. logic low at cfr2<9> disables the oscillator output buffer. connecting clkmodeselect to logic low disables the on-chip oscillator and the oscillator output buffer. with the oscillator disabled, an external oscillator must provide the refclk and/or refclkb signals. for differential operation, these pins are driven with complementary signals. for single- ended operation, a 0.1 f capacitor should be connected between the unused pin and the analog power supply. with the capacitor in place, the clock input pin bias voltage is 1.35 v. in addition, the pll may be used to multiply the reference frequency by an integer value in the range of 4 to 20. table 4 summarizes the clock modes of operation. note that the pll multiplier is controlled via the cfr2<7:3> bits, independent of the cfr1<4> bit. table 4.clock input modes of operation cfr1<4> clkmodeselect cfr2<7:3> oscillator en abled? system clock frequency range (mhz) low high 3 < m < 21 yes f clk = f osc m 80 < f clk < 400 low high m < 4 or m > 20 yes f clk = f osc 20 < f clk < 30 low low 3 < m < 21 no f clk = f osc m 80 < f clk < 400 low low m < 4 or m > 20 no f clk = f osc 10 < f clk < 400 high x x no f clk = 0 n/a
ad9952 rev. 0 | page 14 of 28 dac output the ad9952 incorporates an integrated 14-bit current output dac. unlike most dacs, this output is referenced to avdd, not agnd. two complementary outputs provide a combined full-scale output current (i out ). differential outputs reduce the amount of common-mode noise that might be present at the dac output, offering the advantage of an increased signal-to-noise ratio. the full-scale current is controlled by an external resistor (r set ) connected between the dac_r set pin and the dac ground (agnd_dac). the full-scale current is proportional to the resistor value as follows: out set i r / 19 . 39 = the maximum full-scale output current of the combined dac outputs is 15 ma, but limiting the output to 10 ma provides the best spurious-free dynamic range (sfdr) performance. the dac output compliance range is avdd + 0.5 v to avdd C 0.5 v. voltages developed beyond this range will cause excessive dac distortion and could potentially damage the dac output circuitry. proper attention should be paid to the load termination to keep the output voltage within this compliance range. comparator many applications require a square wave signal rather than a sine wave. for example, in most clocking applications a high slew rate helps to reduce phase noise and jitter. to support these applications, the ad9952 includes an on-chip comparator. the comparator has a bandwidth greater than 200 mhz and a common-mode input range of 1.3 v to 1.8 v. by setting the comparator power-down bit, cfr1<6>, the comparator can be turned off to save on power consumption. serial io port the ad9952 serial port is a flexible, synchronous serial communi- cations port that allows easy interface to many industry-standard microcontrollers and microprocessors. the serial i/o port is com- patible with most synchronous transfer formats, including both the motorola 6905/11 spi? and intel? 8051 ssr protocols. the interface allows read/write access to all registers that configure the ad9952. msb first or lsb first transfer formats are supported. the ad9952s serial interface port can be configured as a single pin i/o (sdio), which allows a 2-wire interface or two unidirectional pins for in/out (sdio/sdo), which in turn enables a 3-wire inter- face. two optional pins, iosync and cs , enable greater flexibility for system design in the ad9952. register map and descriptions the register map is listed in table 5.
ad9952 rev. 0 | page 15 of 28 table 5. register map register name (serial address) bit range (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value <7:0> digital power- down comparator power- down dac power- down clock input power- down external power- down mode not used sync_clk out disable not used 0x00 <15:8> not used not used autoclr phase accum. enable sine output not used clear phase accum. sdio input only lsb first 0x00 <23:16> automatic sync enable software manual sync not used 0x00 control function register no.1 (cfr1) (0x00) <31:24> not used load arr @ i/o ud osk enable auto osk keying 0x00 <7:0> refclk multiplier 0x00 or 0x01, or 0x02 or 0x03: bypass multiplier 0x04 to 0x14: 4 to 20 multiplication vco range charge pump current <1:0> 0x00 <15:8> not used high speed sync enable hardware manual sync enable crystal out pin active not used 0x00 control function register no. 2 (cfr2) (0x01) <23:16> not used 0x00 <7:0> amplitude scale factor register <7:0> 0x00 amplitude scale factor (asf) (0x02) <15:8> auto ramp rate speed control <1:0> amplitude scale factor register <13:8> 0x00 amplitude ramp rate (arr) (0x03) <7:0> amplitude ramp rate register <7:0> 0x00 <7:0> frequency tuning word no. 0 <7:0> 0x00 <15:8> frequency tuning word no. 0 <15:8> 0x00 <23:16> frequency tuning word no. 0 <23:16> 0x00 frequency tuning word (ftw0) (0x04) <31:24> frequency tuning word no. 0 <31:24> 0x00 <7:0> phase offset word no. 0 <7:0> 0x00 phase offset word (pow0) (0x05) <15:8> not used<1:0> phase offset word no. 0 <13:8> 0x00
ad9952 rev. 0 | page 16 of 28 control register bit descriptions control function register no. 1 (cfr1) the cfr1 is used to control the various functions, features, and modes of the ad9952. the functionality of each bit is detailed below. cfr1<31:27>: not used cfr1<26>: amplitude ramp rate load control bit cfr1<26> = 0 (default). the amplitude ramp rate timer is loaded only upon timeout (timer == 1) and is not loaded due to an i/o update input signal. cfr1<26> = 1. the amplitude ramp rate timer is loaded upon timeout (timer == 1) or at the time of an i/o update input signal. cfr1<25>: shaped on-off keying enable bit cfr1<25> = 0 (default). shaped on-off keying is bypassed. cfr1<25> = 1. shaped on-off keying is enabled. when enabled, cfr1<24> controls the mode of operation for this function. cfr1<24>: auto shaped on-off keying enable bit (only valid when cfr1<25> is active high) cfr1<24> = 0 (default). when cfr1<25> is active, a logic 0 on cfr1<24> enables the manual shaped on-off keying opera- tion. each amplitude sample sent to the dac is multiplied by the amplitude scale factor. see the shaped on-off keying sec- tion for details. cfr1<24> = 1. when cfr1<25> is active, a logic 1 on cfr1<24> enables the auto shaped on-off keying operation. toggling the osk pin high will cause the output scalar to ramp up from zero scale to the amplitude scale factor at a rate deter- mined by the amplitude ramp rate. toggling the osk pin low will cause the output to ramp down from the amplitude scale factor to zero scale at the amplitude ramp rate. see the shaped on-off keying section for details. cfr1<23>: automatic synchronization enable bit cfr1<23> = 0 (default). the automatic synchronization feature of multiple ad9952s is inactive. cfr1<23> = 1. the automatic synchronization feature of mul- tiple ad9952s is active. the device will synchronize its internal synchronization clock (sync_clk) to align to the signal pre- sent on the sync_in input. see the synchronizing multiple ad9952s section for details. cfr1<22>: software manual synchronization of multiple ad9952s. cfr1<22> = 0 (default). the manual synchronization feature is inactive. cfr1<22> = 1. the software controlled manual synchroniza- tion feature is executed. the sync_clk rising edge is advanced by one sync_clk cycle and this bit is cleared. to advance the rising edge multiple times, this bit needs to be set for each advance. see the synchronizing multiple ad9952s sec- tion for details. cfr1<21:14>: not used cfr1<13>: auto-clear phase accumulator bit cfr1<13> = 0 (default). the current state of the phase accumu- lator remains unchanged when the frequency tuning word is applied. cfr1<13> = 1. this bit automatically synchronously clears (loads 0s into) the phase accumulator for one cycle upon recep- tion of an i/o update signal. cfr1<12>: sine/cosine select bit cfr1<12> = 0 (default). the angle-to-amplitude conversion logic employs a cosine function. cfr1<12> = 1. the angle-to-a mplitude conversion logic employs a sine function. cfr1<11>: not used cfr1<10>: clear phase accumulator cfr1<10> = 0 (default). the phase accumulator functions as normal. cfr1<10> = 1. the phase accumulator memory elements are cleared and held clear until this bit is cleared. cfr1<9>: sdio input only cfr1<9> = 0 (default). the sdio pin has bidirectional opera- tion (2-wire serial programming mode). cfr1<9> = 1. the serial data i/o pin (sdio) is configured as an input only pin (3-wire serial programming mode). cfr1<8>: lsb first cfr1<8> = 0 (default). msb first format is active. cfr1<8> = 1. the serial interface accepts serial data in lsb first format. cfr1<7>: digital power-down bit cfr1<7> = 0 (default). all digital functions and clocks are active. cfr1<7> = 1. all non-io digital functionality is suspended, lowering the power significantly.
ad9952 rev. 0 | page 17 of 28 cfr1<6>: comparator power-down bit cfr1<6> = 0 (default). the comparator is enabled for operation. cfr1<6> = 1. the comparator is disabled and is in its lowest power dissipation state. cfr1<5>: dac power-down bit cfr1<5> = 0 (default). the dac is enabled for operation. cfr1<5> = 1. the dac is disabled and is in its lowest power dissipation state. cfr1<4>: clock input power-down bit cfr1<4> = 0 (default). the clock input circuitry is enabled for operation. cfr1<4> = 1. the clock input circuitry is disabled and the device is in its lowest power dissipation state. cfr1<3>: external power-down mode cfr1<3> = 0 (default). the external power-down mode selected is the rapid recovery power-down mode. in this mode, when the pwrdwnctl input pin is high, the digital logic and the dac digital logic are powered down. the dac bias circuitry, pll, oscillator, and clock input circuitry are not powered down. cfr1<3> = 1. the external power-down mode selected is the full power-down mode. in this mode, when the pwrdwnctl input pin is high, all functions are powered down. this includes the dac and pll, which take a significant amount of time to power up. cfr1<2>: not used cfr1<1>: sync_clk disable bit cfr1<1> = 0 (default). the sync_clk pin is active. cfr1<1> = 1. the sync_clk pin assumes a static logic 0 state to keep noise generated by the digital circuitry at a mini- mum. however, the synchronization circuitry remains active (internally) to maintain normal device timing. cfr1<0>: not used, leave at 0 control function register no. 2 (cfr2) the cfr2 is used to control the various functions, features, and modes of the ad9952, primarily related to the analog sections of the chip. cfr2<23:12>: not used cfr2<11>: high speed sync enable bit cfr2<11> = 0 (default). the high speed sync enhancement is off. cfr2<11> = 1. the high speed sync enhancement is on. this bit should be set when attempting to use the auto- synchronization feature for sync_clk inputs beyond 50 mhz, (200 msps sysclk). see the synchronizing multiple ad9952s section for details. cfr2<10>: hardware manual sync enable bit cfr2<10> = 0 (default). the hardware manual sync function is off. cfr2<10> = 1. the hardware manual sync function is enabled. while this bit is set, a rising edge on the sync_in pin will cause the device to advance the sync_clk rising edge by one refclk cycle. unlike the software manual sync enable bit, this bit does not self-clear. once the hardware manual sync mode is enabled, it will stay enabled until this bit is cleared. see the synchronizing multiple ad9952s section for details. cfr2<9>: crystal out enable bit cfr2<9> = 0 (default). the crystal out pin is inactive. cfr2<9> = 1. the crystal out pin is active. when active, the crystal oscillator circuitry output drives the crystal out pin, which can be connected to other devices to produce a refer- ence frequency. the oscillator will respond to crystals in the range of 20 mhz to 30 mhz. cfr2<8>: not used cfr2<7:3>: reference clock multiplier control bits this 5-bit word controls the multiplier value out of the clock- multiplier (pll) block. valid values are decimal 4 to 20 (0x04 to 0x14). values entered outside this range will bypass the clock multiplier. see the phase-locked loop (pll) section for details. cfr2<2>: vco range control bit this bit is used to control the range setting on the vco. when cfr2<2> == 0 (default), the vco operates in a range of 100 mhz to 250 mhz. when cfr2<2> == 1, the vco operates in a range of 250 mhz to 400 mhz. cfr2<1:0>: charge pump current control bits these bits are used to control the current setting on the charge pump. the default setting, cfr2<1:0>, sets the charge pump current to the default value of 75 a. for each bit added (01, 10, 11), 25 a of current is added to the charge pump current: 100 a, 125 a, and 150 a.
ad9952 rev. 0 | page 18 of 28 other register descriptions amplitude scale factor (asf) the asf register stores the 2-bit auto ramp rate speed value and the 14-bit amplitude scale factor used in the output shaped keying (osk) operation. in auto osk operation, asf <15:14> tells the osk block how many amplitude steps to take for each increment or decrement. asf<13:0> sets the maximum value achievable by the osk internal multiplier. in manual osk mode, asf<15:14> has no effect. asf <13:0> provides the output scale factor directly. if the osk enable bit is cleared, cfr1<25> = 0, this register has no effect on device operation. amplitude ramp rate (arr) the arr register stores the 8-bit amplitude ramp rate used in the auto osk mode. this register programs the rate at which the amplitude scale factor counter increments or decrements. if the osk is set to manual mode, or if osk enable is cleared, this register has no effect on device operation. frequency tuning word 0 (ftw0) the frequency tuning word is a 32-bit register that controls the rate of accumulation in the phase accumulator of the dds core. its specific role is dependent on the device mode of operation. phase offset word (pow) the phase offset word is a 14-bit register that stores a phase offset value. this offset value is added to the output of the phase accumulator to offset the current phase of the output signal. the exact value of phase offset is given by the following formula: ? ? ? ? ? ? = 360 2 14 pow modes of operation single-tone mode in single-tone mode, the dds core uses a single tuning word. whatever value is stored in ftw0 is supplied to the phase accumulator. this value can only be changed manually, which is done by writing a new value to ftw0 and by issuing an i/o update. phase adjustment is possible through the phase offset register. programming ad9952 features phase offset control a 14-bit phase offset () may be added to the output of the phase accumulator by means of the control registers. this feature provides the user with two different methods of phase control. the first method is a static phase adjustment, where a fixed phase offset is loaded into the appropriate phase offset register and left unchanged. the result is that the output signal is offset by a constant angle relative to the nominal signal. this allows the user to phase align the dds output with some external signal, if necessary. the second method of phase control is where the user regularly updates the phase offset register via the i/o port. by properly modifying the phase offset as a function of time, the user can implement a phase modulated output signal. however, both the speed of the i/o port and the frequency of sysclk limit the rate at which phase modulation can be performed. the ad9952 allows for a programmable continuous zeroing of the phase accumulator as well as a clear and release or auto- matic zeroing function. each feature is individually controlled via the cfr1 bits. cfr1<13> is the automatic clear phase ac- cumulator bit. cfr1<10> clears the phase accumulator and holds the value to zero. continuous clear bit the continuous clear bit is simply a static control signal that, when active high, holds the phase accumulator at zero for the entire time the bit is active. when the bit goes low, inactive, the phase accumulator is allowed to operate. clear and release function when set, the auto-clear phase accumulator clears and releases the phase accumulator upon receiving an i/o update. the automatic clearing function is repeated for every subsequent i/o update until the appropriate auto-clear control bit is cleared. shaped on-off keying the shaped on-off keying function of the ad9952 allows the user to control the ramp-up and ramp-down time of an on-off emission from the dac. this function is used in burst trans- missions of digital data to reduce the adverse spectral impact of short, abrupt bursts of data. auto and manual shaped on-off keying modes are supported. the auto mode generates a linear scale factor at a rate deter- mined by the amplitude ramp rate (arr) register controlled by an external pin (osk). manual mode allows the user to directly control the output amplitude by writing the scale factor value into the amplitude scale factor (asf) register. the shaped on-off keying function may be bypassed (disabled) by clearing the osk enable bit (cfr1<25> = 0). the modes are controlled by two bits located in the most sig- nificant byte of the control function register (cfr). cfr1<25> is the shaped on-off keying enable bit. when cfr1<25> is set, the output scaling function is enabled and cfr1<25> bypasses the function. cfr1<24> is the internal shaped on-off keying active bit. when cfr1<24> is set, internal shaped on-off keying mode is active; cfr1<24> is cleared, external shaped on-off keying mode is active. cfr1<24> is a dont care if the shaped on-off keying enable bit (cfr1<25>) is cleared. the power up condition is shaped on-off keying disabled (cfr1<25> = 0). figure 20 shows the block diagram of the osk circuitry.
ad9952 rev. 0 | page 19 of 28 auto shaped on-off keying mode operation the auto shaped on-off keying mode is active when cfr1<25> and cfr1<24> are set. when auto shaped on-off keying mode is enabled, a single-scale factor is internally generated and applied to the multiplier input for scaling the output of the dds core block (see figure 20). the scale factor is the output of a 14-bit counter that increments/decrements at a rate determined by the contents of the 8-bit output ramp rate register. the scale factor increases if the osk pin is high and decreases if the osk pin is low. the scale factor is an unsigned value such that all 0s multiply the dds core output by 0 (decimal) and 0x3fff mul- tiplies the dds core output by 16383 (decimal). for those users who use the full amplitude (14-bits) but need fast ramp rates, the internally generated scale factor step size is controlled via the asf<15:14> bits. table 6 describes the increment/decrement step size of the internally generated scale factor per the asf<15:14> bits. a special feature of this mode is that the maximum output amplitude allowed is limited by the contents of the amplitude scale factor register. this allows the user to ramp to a value less than full scale. table 6. auto-scale factor internal step size asf<15:14> (binary) increment/decrement size 00 1 01 2 10 4 11 8 osk ramp rate timer the osk ramp rate timer is a loadable down counter, which generates the clock signal to the 14-bit counter that generates the internal scale factor. the ramp rate timer is loaded with the value of the asfr every time the counter reaches 1 (decimal). this load and countdown operation continues for as long as the timer is enabled, unless the timer is forced to load before reach- ing a count of 1. if the load osk timer bit (cfr1<26>) is set, the ramp rate timer is loaded upon an i/o update or upon reaching a value of 1. the ramp timer can be loaded before reaching a count of 1 by three methods. the first method of loading is by changing the osk input pin. when the osk input pin changes state, the asfr value is loaded into the ramp rate timer, which then proceeds to count down as normal. the second method in which the sweep ramp rate timer can be loaded before reaching a count of 1 is if the load osk timer bit (cfr1<26>) is set and an i/o update is issued. the last method in which the sweep ramp rate timer can be loaded before reaching a count of 1 is when going from the inactive auto shaped on-off keying mode to the active auto shaped on-off keying mode; that is, when the sweep enable bit is being set. 03374-0-005 osk pin load osk timer cfr1<26> sync_clk auto desk enable cfr1<24> to dac auto scale factor generator ramp rate timer clock dds core osk enable cfr<25> amplitude scale factor register (asf) 0 0 1 01 01 hold inc/dec enable out cos(x) amplitude ramp rate register (asf) up/dn data load en figure 20. on-off shaped keying, block diagram
ad9952 rev. 0 | page 20 of 28 external shaped on-off keying mode operation the external shaped on-off keying mode is enabled by writing cfr1<25> to a logic 1 and writing cfr1<24> to a logic 0. when configured for external shaped on-off keying, the content of the asfr becomes the scale factor for the data path. the scale factors are synchronized to sync_clk via the i/o update functionality. synchronization; register updates (i/o update) functionality of the sync_clk and i/o update data into the ad9952 is synchronous to the sync_clk signal (supplied externally to the user on the sync_clk pin). the i/o update pin is sampled on the rising edge of the sync_clk. internally, sysclk is fed to a divide-by-4 frequency divider to produce the sync_clk signal. the sync_clk signal is pro- vided to the user on the sync_clk pin. this enables synchro- nization of external hardware with the devices internal clocks. this is accomplished by forcing any external hardware to obtain its timing from sync_clk. the i/o update signal coupled with sync_clk is used to transfer internal buffer contents into the control registers of the device. the combination of the sync_clk and i/o update pins provides the user with constant latency relative to sysclk, and also ensures phase continuity of the analog output signal when a new tuning word or phase offset value is asserted. figure 21 demonstrates an i/o update timing cycle and synchronization. notes to synchronization logic: 1) the i/o update signal is edge detected to generate a single rising edge clock signal that drives the register bank flops. the i/o update signal has no constraints on duty cycle. the minimum low time on i/o update is one sync_clk clock cycle. 2) the i/o update pin is set up and held around the rising edge of sync_clk and has zero hold time and 4 ns setup time. 03374-0-006 sysclk sdi sync_clk disable 10 0 sclk to core logic cs osk d q profile<1:0> d q i/o update d q 4 sync_clk gating edge detection logic register memory i/o buffer latches figure 21. i/o synchronization block diagram
ad9952 rev. 0 | page 21 of 28 sync_clk sysclk ab data 2 data 3 data 1 data in registers data in i/o buffers data 1 data 2 data 3 i/o update the device registers an i/o update at point a. the data is transferred from the asynchronously loaded i/o buffers at point b. 03374-0-007 figure 22. i/o synchronization timing diagram synchronizing multiple ad9952s the ad9952 product allows easy synchronization of multiple ad9952s. there are three modes of synchronization available to the user: an automatic synchronization mode, a software controlled manual synchronization mode, and a hardware controlled manual synchronization mode. in all cases, when a user wants to synchronize two or more devices, the following considerations must be observed. first, all units must share a common clock source. trace lengths and path impedance of the clock tree must be designed to keep the phase delay of the dif- ferent clock branches as closely matched as possible. second, the i/o update signals rising ed ge must be provided synchro- nously to all devices in the system. finally, regardless of the internal synchronization method used, the dvdd_i/o supply should be set to 3.3 v for all devices that are to be synchronized. avdd and dvdd should be left at 1.8 v. in automatic synchronization mode, one device is chosen as a master; the other device(s) will be slaved to this master. when configured in this mode, the slaves will automatically synchro- nize their internal clocks to the sync_clk output signal of the master device. to enter automatic synchronization mode, set the slave devices automatic synchronization bit (cfr1<23> = 1). connect the sync_in input(s) to the master sync_clk output. the slave device will continuously update the phase relationship of its sync_clk until it is in phase with the sync_in input, which is the sync_clk of the master device. when attempting to synchronize devices running at sysclk speeds beyond 250 msps, the high speed sync enhancement enable bit should be set (cfr2<11> = 1). in software manual synchronization mode, the user forces the device to advance the sync_clk rising edge one sysclk cycle (1/4 sync_clk period). to activate the manual synchro- nization mode, set the slave devices software manual synchroni- zation bit (cfr1<22> = 1). the bit (cfr1<22>) will be cleared immediately. to advance the rising edge of the sync_clk multi- ple times, this bit will need to be set multiple times. in hardware manual synchronization mode, the sync_in input pin is configured such that it will now advance the rising edge of the sync_clk signal each time the device detects a rising edge on the sync_in pin. to put the device into hard- ware manual synchronization mode, set the hardware manual synchronization bit (cfr2<10> = 1). unlike the software man- ual synchronization bit, this bit does not self-clear. once the hardware manual synchronization mode is enabled, all rising edges detected on the sync_in input will cause the device to advance the rising edge of the sync_clk by one sysclk cycle until this enable bit is cleared (cfr2<10> = 0). using a single crystal to drive multiple ad9952 clock inputs the ad9952 crystal oscillator output signal is available on the crystal out pin, enabling one crystal to drive multiple ad9952s. in order to drive multiple ad9952s with one crystal, the crystal out pin of the ad9952 using the external crystal should be connected to the refclk input of the other ad9952. the crystal out pin is static until the cfr2<9> bit is set, enabling the output. the drive strength of the crystal out pin is typically very low, so this signal should be buffered prior to using it to drive any loads. serial port operation with the ad9952, the instruction byte specifies read/write operation and the register address. serial operations on the ad9952 occur only at the register level, not the byte level. for the ad9952, the serial port controller recognizes the instruction byte register address and automatically generates the proper register byte address. in addition, the controller expects that all bytes of that register will be accessed. it is required that all bytes of a register be accessed during serial i/o operations, with one exception. the iosync function can be used to abort an i/o operation, thereby allowing some, but not all bytes to be accessed.
ad9952 rev. 0 | page 22 of 28 there are two phases to a communication cycle with the ad9952. phase 1 is the instruction cycle, which is the writing of an instruction byte into the ad9952, coincident with the first eight sclk rising edges. the instruction byte provides the ad9952 serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write and the serial address of the register being accessed. (note that the serial address of the register being accessed is not the same address as the bytes to be written. see the example operation section for details.) the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the ad9952. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the ad9952 and the system controller. the number of bytes transferred during phase 2 of the communication cycle is a function of the register being accessed. for example, when accessing the control function register no. 2, which is three bytes wide, phase 2 requires that three bytes be transferred. if accessing the frequency tuning word, which is four bytes wide, phase 2 requires that four bytes be transferred. after transferring all data bytes per the instruc- tion, the communication cycle is completed. at the completion of any communication cycle, the ad9952 serial port controller expects the next eight rising sclk edges to be the instruction byte of the next communication cycle. all data input to the ad9952 is registered on the rising edge of sclk. all data is driven out of the ad9952 on the falling edge of sclk. figure 23 through figure 26 are useful in understand- ing the general operation of the ad9952 serial port. 03374-0-008 i 6 i 5 i 4 i 3 i 2 i 1 d 5 d 4 d 3 d 2 d 1 d 0 i 0 d 7 d 6 i 7 instruction cycle s clk sdio data transfer cycle cs figure 23. serial port write timingCclock stall low 03374-0-009 i 6 i 5 i 4 i 3 i 2 i 1 i 0 don't care i 7 instruction cycle s clk sdio data transfer cycle d o 5 d o 4 d o 3 d o 2 d o 1 d o 0 d o 7 d o 6 sdo cs figure 24. 3-wire serial port read timingCclock stall low 03374-0-010 i 6 i 5 i 4 i 3 i 2 i 1 d 5 d 4 d 3 d 2 d 1 d 0 i 0 d 7 d 6 i 7 instruction cycle s cl k sdio data transfer cycle cs figure 25. serial port write timingCclock stall high 03374-0-011 i 6 i 5 i 4 i 3 i 2 i 1 d o 5 d o 4 d o 3 d o 2 d o 1 d o 0 i 0 d o 7 d o 6 i 7 instruction cycle s clk sdio data transfer cycle cs figure 26. 2-wire serial port read timingclock stall high
ad9952 rev. 0 | page 23 of 28 instruction byte the instruction byte contains the following information: table 7. msb d6 d5 d4 d3 d2 d1 lsb r/ w x x a4 a3 a2 a1 a0 r/ w bit 7 of the instruction byte determines whether a read or write data transfer will occur after the instruction byte write. logic high indicates read operation. logic 0 indicates a write operation. x, xbits 6 and 5 of the instruction byte are dont care. a4, a3, a2, a1, a0bits 4, 3, 2, 1, 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. serial interface port pin description sclkserial clock. the serial clock pin is used to synchronize data to and from the ad9952 and to run the internal state machines. sclk maximum frequency is 25 mhz. csbchip select bar. csb is active low input that allows more than one device on the same serial communications line. the sdo and sdio pins will go to a high impedance state when this input is high. if driven high during any communications cycle, that cycle is suspended until cs is reactivated low. chip select can be tied low in systems that maintain control of sclk. sdioserial data i/o. data is always written into the ad9952 on this pin. however, this pin can be used as a bidirectional data line. bit 7 of register address 0x00 controls the configuration of this pin. the default is logic 0, which configures the sdio pin as bidirectional. sdoserial data out. data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the ad9952 operates in a single bidirectional i/o mode, this pin does not output data and is set to a high imped- ance state. iosyncit synchronizes the i/o port state machines without affecting the addressable registers contents. an active high in- put on the iosync pin causes the current communication cycle to abort. after iosync returns low (logic 0), another communication cycle may begin, starting with the instruction byte write. msb/lsb transfers the ad9952 serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by the control register 0x00 <8> bit. the default value of control register 0x00 <8> is low (msb first). when control register 0x00 <8> is set high, the ad9952 serial port is in lsb first format. the instruction byte must be written in the format indicated by control register 0x00 <8>. if the ad9952 is in lsb first mode, the instruction byte must be written from least significant bit to most significant bit. for msb first operation, the serial port controller will generate the most significant byte (of the specified register) address first followed by the next lesser significant byte addresses until the i/o operation is complete. all data written to (read from) the ad9952 must be (will be) in msb first order. if the lsb mode is active, the serial port controller will generate the least signifi- cant byte address first followed by the next greater significant byte addresses until the i/o operation is complete. all data written to (read from) the ad9952 must be (will be) in lsb first order. example operation to write the amplitude scale factor register in msb first format, apply an instruction byte of 0x02 [serial address is 00010(b)]. from this instruction, the internal controller will generate an internal byte address of 0x07 (see the register map) for the first data byte written and an internal address of 0x08 for the next byte written. since the amplitude scale factor register is two bytes wide, this ends the communication cycle. to write the amplitude scale factor register in lsb first format, apply an instruction byte of 0x40. from this instruction, the internal controller will generate an internal byte address of 0x08 (see the register map) for the first data byte written and an internal address of 0x07for the next byte written. since the amplitude scale factor register is two bytes wide, this ends the communication cycle. power-down functions of the ad9952 the ad9952 supports an externally controlled or hardware power-down feature as well as the more common software pro- grammable power-down bits found in previous adi dds products. the software control power-down allows the dac, comparator, pll, input clock circuitry, and digital logic to be individually powered down via unique control bits (cfr1<7:4>). with the exception of cfr1<6>, these bits are not active when the exter- nally controlled power-down pin (pwrdwnctl) is high. external power-down control is supported on the ad9952 via the pwrdwnctl input pin. when the pwrdwnctl input pin is high, the ad9952 will enter a power-down mode based on the cfr1<3> bit. when the pwrdwnctl input pin is low, the external power-down control is inactive.
ad9952 rev. 0 | page 24 of 28 when the cfr1<3> bit is 0 and the pwrdwnctl input pin is high, the ad9952 is put into a fast recovery power-down mode. in this mode, the digital logic and the dac digital logic are powered down. the dac bias circuitry, comparator, pll, oscil- lator, and clock input circuitry is not powered down. the com- parator can be individually powered down by setting the com- parator power-down bit, cfr1<6> = 1. when the cfr1<3> bit is high, and the pwrdwnctl input pin is high, the ad9952 is put into the full power-down mode. in this mode, all functions are powered down. this includes the dac and pll, which take a significant amount of time to power up. when the pwrdwnctl input pin is high, the individual power-down bits (cfr1<7>, <5:4>) are invalid (dont care) and unused. when the pwrdwnctl input pin is low, the individual power-down bits control the power-down modes of operation. note that the power-down signals are all designed such that a logic 1 indicates the low power mode and a logic 0 indicates the active or power-up mode. table 8 indicates the logic level for each power-down bit that drives out of the ad9952 core logic to the analog section and the digital clock generation section of the chip for the external power-down operation. layout considerations for the best performance, the following layout guidelines should be observed. always provide the analog power supply (avdd) and the digital power supply (dvdd) on separate supplies, even if just from two different voltage regulators driven by a common supply. likewise, the ground connections (agnd, dgnd) should be kept separate as far back to the source as possible (i.e., separate the ground planes on a local- ized board, even if the grounds connect to a common point in the system). bypass capacitors should be placed as close to the device pin as possible. usually, a multitiered bypassing scheme consisting of a small high frequency capacitor (100 pf) placed close to the supply pin and progressively larger capacitors (0.1 f, 10 f) placed further away from the actual supply source works best. table 8. power-down control functions control mode active description pwrdwnctl = 0 cfr1<3> dont care software control digital power-down = cfr1<7> comparator power-down = cfr1<6> dac power-down = cfr1<5> input clock power-down = cfr1<4> pwrdwnctl = 1 cfr1<3> = 0 external control, fast recovery power-down mode digital power-down = 1b1 comparator power-down = 1b0 or cfr1<6> dac power-down = 1b0 input clock power-down = 1b0 pwrdwnctl = 1 cfr1<3> = 1 external control, full power-down mode digital power-down = 1b1 comparator power-down = 1b1 dac power-down = 1b1 input clock power-down = 1b1
ad9952 rev. 0 | page 25 of 28 suggested application circuits 03358-0-003 lpf ad9952 refcl k rf/if input modulated/ demodulated signal figure 27. synchronized lo fo r upconversion/d own conversion 03358-0-004 filter phase comparator loop filter ad9952 tuning world ref signal vco figure 28. digitally programmable divide-by-n function in pll 03358-0-006 tuning word cmos level clock ad9952 dds ad9952 on-chip comparator iout iout lpf lpf figure 29. frequency agile clock generator 03358-0-005 saw crystal frequency tuning word phase offset word 2 i/i-bar baseband frequency tuning word phase offset word 1 q/q-bar baseband sync in ad9952 dds refclk refclk refclk lpf sync out crystal out ad9952 dds iout iout lpf iout iout rf out figure 30. two ad9952s synchronized to provide i and q carriers with independent phase offsets for nulling
ad9952 rev. 0 | page 26 of 28 outline dimensions bottom view (pins up) top view (pins down) 0.50 bsc 0.27 0.22 0.17 9.00 bsc sq 7.00 bsc sq 37 48 1 13 12 24 25 36 view a 0.75 0.60 0.45 view a 1.05 1.00 0.95 7 3.5 0 seating plane 0.15 0.05 exposed pad 2.00 sq 1.20 ma x compliant to jedec standards ms-026-abc figure 31. 48-lead thin plastic quad flat package, exposed pad [tqfp/ep] (sv-48)dimensions shown in millimeters esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warningplease note that this device in its current form does not meet analog devices standard requirements for esd as measured against the charged device model (cdm). as such, special care should be used when handling this product, especially in a manufacturing environment. analog devices will provide a more esd-hardy product in the near future at which time this warn- ing will be removed from this data sheet. ordering guide model temperature range package description package outline ad9952ysv C40c to +105c 48-lead thin plastic qu ad flat package, expo sed pad, tqfp/ep sv-48 AD9952YSV-REEL7 C40c to +105c 48-lead tqfp/ep (500 piece reel7) sv-48 ad9952/pcb evaluation board
ad9952 rev. 0 | page 27 of 28 notes
ad9952 rev. 0 | page 28 of 28 notes ? 2003 analog devices, inc. all rights reserved. trademarks and regis- tered trademarks are the property of their respective owners. d03358-0-12/03(0)

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